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isolated precision half-bridge driver, 4.0 a output data sheet adum7223 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2013C2014 analog devices, inc. all rights reserved. technical support www.analog.com features 4.0 a peak output current working voltage high-side or low-side relative to input: 565 v peak high-side to low-side differential: 700 v peak high frequency operation: 1 mhz maximum precise timing characteristics 64 ns maximum propagation delay 8.5 ns maximum channel-to-channel matching 3.0 v to 5.5 v input voltage 4.5 v to 18 v output drive uvlo supply at 2.8 v v dd1 a version uvlo, v dda and v ddb (v dd2 ) at 4.1 v b version uvlo, v dda and v ddb at 6.9 v c version uvlo, v dda and v ddb at 10.5 v cmos input logic levels high common-mode transient immunity: >25 kv/s high junction temperature operation: 125c default low output 5 mm 5 mm, 13-terminal lga applications switching power supplies isolated igbt/mosfet gate drives industrial inverters general description the adum7223 is a 4.0 a isolated, half-bridge gate driver that employs analog devices, inc., i coupler? technology to provide independent and isolated high-side and low-side outputs. combining high speed cmos and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as the combination of pulse transformers and non-isolated gate drivers. by integrating the isolator and driver in a single package, propagation delay is a maximum of only 64 ns, and the propagation skew from channel to channel is a maximum of only 12 ns at 12 v. the adum7223 provides two independent isolation channels. the adum7223 operates with an input supply ranging from 3.0 v to 5.5 v, providing compatibility with lower voltage systems. the outputs operate in a wide range from 4.5 v to 18 v with three output voltage versions available. the 5 mm 5 mm, lga package provides 565 v operating voltage from input to output and 700 v from output to output. in comparison to gate drivers employing high voltage level translation methodologies, this gate driver offers the benefit of true, galvanic isolation between the input and each output. as a result, this gate driver provides reliable control over the switching characteristics of igbt/mosfet configurations over a wide range of positive or negative switching voltages. functional block diagram figure 1. encode decode encode decode disable nc nc v dd1 gnd b v ddb v ob 5 6 7 10 9 gnd 1 4 gnd a 3 11 v ib v oa 2 12 v ia v dda 1 13 8 nc = no connect adum7223 11740-001
adum7223* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ad-fmcmotcon2-ebz evaluation board ? adum7223 evaluation board documentation data sheet ? adum7223: isolated precision half-bridge driver, 4.0 a output data sheet user guides ? ug-657: evaluation board for the adum7223 i coupler, 4 a, isolated precision half bridge driver reference materials informational ? overcoming limitations of optocoupler and high voltage gate driver solutions design resources ? adum7223 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all adum7223 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
adum7223 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 5 v operation ................................ 3 electrical characteristics 3.3 v operation ............................ 4 package characteristics ............................................................... 6 insulation and safety - related specifications ............................ 6 recommended operating conditions ...................................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ..............................8 typical performance characteristics ..............................................9 applications information .............................................................. 11 printed circuit board (pcb) layout ....................................... 11 propagation delay - related parameters ................................... 11 thermal limitations and switch load characteristics ......... 11 output load characteristics ..................................................... 11 dc correctness and magnetic field immunity ..................... 12 power consumption .................................................................. 13 insulation lifetime ..................................................................... 13 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 4/14 rev. 0 to rev. a added b model and c model ...................................... throughout changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to printed circuit board (pcb) layout section and thermal limitations and switch load characteristics section .............................................................................................. 1 1 changes to ordering guide .......................................................... 1 4 10/1 3 revision 0: initial version rev. a | page 2 of 16
data sheet adum7223 specifications electrical character istics 5 v operation all voltages are relative to their respective ground. 4.5 v v dd1 5.5 v , 4.5 v v dd2 18 v , unless stated otherwise. all minimum/maximum specifications apply over t j = ? 40 c to + 125 c. all typical specifications are at t a = 25c, v dd1 = 5 v, v dd2 = 1 2 v. switching specifications are tested with cmos signal levels. table 1. parameter symbol min typ max unit test conditions /comments dc specifications input supply current, quiescent i ddi (q) 1. 4 2.4 ma output supply current per channel, quiescent i ddo (q) 2.3 3.5 ma supply current at 1 mhz v dd1 supply current i dd1 (q) 1.6 2.5 ma up to 1 mhz, no load v dd a /v ddb supply current i dd a (q) , i ddb (q) 5.6 8.0 ma up to 1 mhz, no load input currents i ia , i ib ? 1 +0.01 +1 a 0 v v ia , v ib v dd1 logic high input threshold v ih 0.7 v dd1 v logic low input threshold v il 0.3 v dd1 v logic high output voltages v oah , v o b h v dd2 ? 0. 1 v dd2 v i ox = ?20 ma, v ix = v ixh logic low output voltages v oal , v obl 0.0 0.15 v i ox = 20 ma, v ix = v ixl undervoltage lockout, v dd1 supply positive going threshold v dd1uv+ 2.8 v negative going threshold v dd1uv? 2.6 v hysteresis v dd1uvh 0.2 v undervoltage lockout, v dd2 supply positive going threshold v dd2uv+ 4.1 4.4 v a - grade negative going threshold v dd2uv ? 3.2 3.6 v a - grade hysteresis v dd2uvh 0. 5 v a - grade positive going threshold v dd2uv+ 6.9 7.4 v b - grade negative going threshold v dd2uv? 5.7 6.2 v b - grade hysteresis v dd2uvh 0.7 v b - grade positive going threshold v dd2uv+ 10.5 11.1 v c - grade negative going threshold v dd2uv? 9.0 9.6 v c - grade hysteresis v dd2uvh 0. 9 v c - grade output short - circuit pulsed current 1 i oa(sc) ,i ob(sc) 2.0 4.0 a v dd2 = 1 2 v output source resistance r oa , r ob 0.25 0.95 1.5 v dd2 = 12 v , i ox = ?250 ma output sink resistance r oa , r ob 0.55 0.6 1.35 v dd2 = 12 v , i ox = 250 ma thermal shutdown temperatures junction temperature shutdown rising edge t jr 150 c junction temperature shutdown falling edge t jf 140 c switching specifications s ee figure 16 pulse width 2 pw 50 ns c l = 2 nf, v dd2 = 12 v maximum data rate 3 1 mhz c l = 2 nf, v dd2 = 12 v propagation delay 4 t dhl , t dlh 19 40 62 ns c l = 2 nf, v dd2 = 12 v adum7223a 25 4 6 68 ns c l = 2 nf, v dd2 = 4.5 v propagation delay skew 5 t psk 12 ns c l = 2 nf, v dd2 = 12 v rev. a | page 3 of 16
adum7223 data sheet rev. a | page 4 of 16 parameter symbol min typ max unit test conditions/comments channel-to-channel matching 6 t pskcd v dd2 = 12 v 1 8.5 ns c l = 2 nf v dd2 = 4.5 v 1 8.5 ns c l = 2 nf; a-grade only output rise/fall time (10% to 90%) t r /t f 1 12 24 ns c l = 2 nf, v dd2 = 12 v dynamic input supply current per channel i ddi (d) 0.05 ma/mbps v dd2 = 12 v dynamic output supply current per channel i ddo (d) 1.65 ma/mbps v dd2 = 12 v refresh rate f r 1.2 mbps v dd2 = 12 v 1 short-circuit duration less than 1 s. average power must co nform to the limit shown under the absolute maximum ratings. 2 the minimum pulse width is the shortest pulse width at which the specified timin g parameter is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 4 t dlh propagation delay is measured from the time of the input rising logic high threshold, v ih , to the output rising 10% level of the v ox signal. t dhl propagation delay is measured from the input falling logic low threshold, v il , to the output falling 90% threshold of the v ox signal. see figure 16 for waveforms of propagation delay parameters. 5 t psk is the magnitude of the worst-case difference in t dlh and/or t dhl that is measured between adum7223 units at the same operating temperature, supply voltages, and output load within the recommended op erating conditions. see figure 16 for wave forms of propagatio n delay parameters. 6 channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. electrical characteristics3.3 v operation all voltages are relative to their respective ground. 3.0 v v dd1 3.6 v, 4.5 v v dd2 18 v, unless stated otherwise. all minimum/maximum specifications apply over t j = ?40c to 125c. all typical specifications are at t a = 25c, v dd1 = 3.3 v, v dd2 = 12 v. switching specifications are tested with cmos signal levels. table 2. parameter symbol min typ max unit test conditions/comments dc specifications input supply current, quiescent i ddi (q) 0.87 1.4 ma output supply current per channel, quiescent i ddo (q) 2.3 3.5 ma supply current at 1 mhz v dd1 supply current i dd1 (q) 1.1 1.5 ma up to 1 mhz, no load v dda /v ddb supply current i dda (q) , i ddb (q) 5.6 8.0 ma up to 1 mhz, no load input currents i ia , i ib ?1 +0.01 +1 a 0 v v ia , v ib v dd1 logic high input threshold v ih 0.7 v dd1 v logic low input threshold v il 0.3 v dd1 v logic high output voltages v oah , v oah v dd2 ? 0.1 v dd2 v i ox = ?20 ma, v ix = v ixh logic low output voltages v oal , v obl 0.0 0.15 v i ox = 20 ma, v ix = v ixl undervoltage lockout, v dd1 supply positive going threshold v dd1uv+ 2.8 v negative going threshold v dd1uv? 2.6 v hysteresis v dd1uvh 0.2 v undervoltage lockout, v dd2 supply positive going threshold v dd2uv+ 4.1 4.4 v a-grade negative going threshold v dd2uv? 3.2 3.6 v a-grade hysteresis v dd2uvh 0.5 v a-grade positive going threshold v dd2uv+ 6.9 7.4 v b-grade negative going threshold v dd2uv? 5.7 6.2 v b-grade hysteresis v dd2uvh 0.7 v b-grade positive going threshold v dd2uv+ 10.5 11.2 v c-grade negative going threshold v dd2uv? 9.0 9.6 v c-grade hysteresis v dd2uvh 0.9 v c-grade output short-circuit pulsed current 1 i oa(sc) , i ob(sc) 2.0 4.0 a v dd2 = 12 v output source resistance r oa , r ob 0.25 0.95 1.5 v dd2 = 12 v, i ox = ?250 ma output sink resistance r oa , r ob 0.55 0.6 1.35 v dd2 = 12 v, i ox = 250 ma
data sheet adum7223 parameter symbol min typ max unit test conditions /comments thermal shutdown temperatures junction temperature shutdown rising edge t jr 150 c junction temperature shutdown falling edge t jf 140 c switching specifications s ee figure 16 pulse width 2 pw 50 ns c l = 2 nf, v dd2 = 1 2 v maximum data rate 3 1 mhz c l = 2 nf, v dd2 = 1 2 v propagation delay 4 t dhl , t dlh 25 44 64 ns c l = 2 nf, v dd2 = 1 2 v adum7223a 28 49 71 ns c l = 2 nf, v dd2 = 4.5 v propagation delay skew 5 t psk 12 ns c l = 2 nf, v dd2 = 1 2 v channel -to - channel matching 6 v dd2 = 12 v t pskcd 1 8.5 ns c l = 2 nf v dd2 = 4.5 v t pskcd 1 8.5 ns c l = 2 nf ; a - grade only output rise/fall time (10% to 90%) t r /t f 1 12 24 ns c l = 2 nf, v dd2 = 1 2 v dynamic input supply current per channel i ddi (d) 0. 05 ma/mbps v dd2 = 1 2 v dynamic output supply current per channel i ddo (d) 1.65 ma/mbps v dd2 = 1 2 v refresh rate f r 1.1 mbps v dd2 = 12 v 1 short - c ircuit duration less than 1 s . average power must conform to the limit shown under the absolute maximum ratings . 2 the minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed . 3 the maximum data rate is the fastest data rate at which the specified timing parameter is guaranteed. 4 t dlh propagation delay is measured from the time of the input rising logic high threshold, v ih , to the output rising 10% level of the v ox signal. t dhl propagation delay is measured from the input falling logic low threshold, v il , to the output falling 90% thre shold of the v ox signal. see figure 16 for waveforms of propagation delay parameters. 5 t psk is the magnitude of the worst - case difference in t dlh and/or t dhl that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. see figure 16 for waveforms o f propagation delay parameters. 6 c hannel - to - channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the sa me side of the isolation barrier. rev. a | page 5 of 16
adum7223 data sheet package characterist ics table 3. parameter symbol min typ max unit test conditions /comments resistance (input -to - output) r i- o 10 12 capacitance (input -to - output) c i- o 2.0 pf f = 1 mhz input capacitance c i 4.0 pf ic junction -to - ambient thermal resistance ja 96.3 c/w ic junction -to - case thermal resistance jc 43.2 c/w insulation and safet y - related specificatio ns table 4. parameter symbol value unit test conditions /comments functional dielectric insulation voltage 1 2500 v rms 1 minute duration minimum external air gap (clearance) l(i01) 3.5 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 3.5 min mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti > 400 v din iec 112/vde 0303 part 1 isolation group ii material group (din vde 0110, 1/89, table 1) 1 insulation voltage guaranteed by d esign, not teste d in production. insulation is similar in structure to devices that are tested to 5 kv rms in production. figure 2 . thermal derating curve recommended operatin g conditions table 5. parameter symbol min max unit operating junction temperature t j ? 40 +125 c supply voltages 1 v dd1 3.0 5.5 v v dda , v ddb 4.5 18 v maximum input signal rise and fall times t v ia, t v ib 1 ms common - mode transient static 2 ? 50 +50 kv/s common - mode transient immunity dynamic 3 ? 25 + 25 kv/s 1 all voltages are relative to their respective ground. see the applications i nformation section for information on immunity to external magnetic fields. 2 static c ommon - m ode t ransient i mmunity is defined as the largest dv/dt between gnd 1 and gnd a / gnd b w ith inputs held either high or low such that the output voltage remains either above 0.8 v dd2 for v ia /v ib = high, or 0.8 v for v ia /v ib = low. operation with transients above recommended levels can cause momentary data upsets. 3 dynamic c ommon - m ode t ransient i mmunity is defined as the largest dv/dt between gnd 1 and gnd a / gnd b with switching edge coincident with the transient test pulse. operation with transients above recommended levels can cause momentary data upsets. 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 50 100 150 200 safe limiting power (w) ambient temper a ture (oc) 1 1740-002 rev. a | page 6 of 16
data sheet adum7223 absolute maximum rat ings ambient temperature = 25c, unless otherwise noted. table 6. parameter symbol rating storage temperature t st ? 55c to +150 c operating junction temperature t j ? 40c to +150c supply voltages 1 v dd1 ? 0.3 v to +6.0 v v dd2 ? 0.3 v to +20 v input voltage 1, 2 v ia , v ib ? 0.3 v to v ddi + 0.3 v output voltage 1, 2 v oa , v ob ? 0.3 to v ddo + 0.3 v average output current, per pin 3 i o ? 35 ma to + 35 ma common - mode transients 4 cm h , cm l ? 100 kv/s to +100 kv/s 1 all voltages are relative to their respective ground. 2 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. 3 see figure 2 for information on maximum allowable curr ent for various temperatures. 4 refers to common - mode transients across the insulation barrier. common - mode transients exceeding the absolute maximum rating can cause latch - up or permanent damage. stresses above those listed under absolute maximum ratin gs may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maxim um rating conditions for extended periods may affect device reliability. esd caution table 7. maximum continuous working voltage 1 parameter max unit constraint ac voltage, bipolar waveform 565 v peak 50- year minimum lifetime ac voltage, unipolar waveform functional insulation 1131 v peak 50- year minimum lifetime dc voltage functional insulation 1131 v peak 50 - year minimum lifetime 1 refers to continuous voltage magnitude imposed across the isolation barrier. see the insulation lifetime section for more details. table 8 . truth table (positive logic) 1 disable v ia inpu t v ib input v dd1 state v dda /v ddb state v oa output v ob output notes l l l powered powered l l outputs return to the input state within 1 s of disable = set to low . l l h powered powered l h outputs return to the input state within 1 s of disable = set to low . l h l powered powered h l outputs return to the input state within 1 s of disable = set to low . l h h powered powered h h outputs return to the input state within 1 s of disable = set to low . h x x powered powered l l outputs take on default low state within 3 s of disable = set to high. l l l unpowered powered l l outputs return to the input state within 1 s of v dd1 power restoration. x x x powered unpowered indeterminate indeterminate outputs retu rn to the input state within 50 s of v dda /v ddb power restoration. 1 x = dont care. rev. a | page 7 of 16
adum7223 data sheet pin configuration an d function descripti ons figure 3 . pin configuration table 9. pin function descriptions pin no. mnemonic description 1 gnd 1 ground reference for input logic signals. 2 v ia logic input a. 3 v ib logic input b. 4, 6 nc no connect. no t internally connected. 5 disable input disable. disables the isolator inputs and refresh circuits. outputs take on default low state. 7 v dd1 input supply voltage. 8 gnd b ground reference for output b. 9 v ob output b. 10 v ddb output b supply voltage. 11 gnd a ground reference for output a. 12 v oa output a. 13 v dda output a supply voltage. 11740-003 v ia gnd 1 v ib nc disable nc = no connect. not internally connected. nc adum7223 top view (not to scale) 1 2 3 4 5 6 7 13 12 11 10 9 8 v dd1 v oa v dda gnd a v ddb v ob gnd b rev. a | page 8 of 16
data sheet adum7223 typical perfo r mance characteristic s figure 4 . output waveform for 2 nf load with 12 v output supply figure 5 . output matching and rise time waveforms for 2 nf load with 12 v output supply figure 6 . typical i dd1 supply current vs. frequency figure 7 . typical i dda /i ddb supply current vs. frequency with 2 nf load figure 8 . typical propagation delay vs. junction temperature figure 9 . typical propagation delay vs. input supply voltage, v dda /v ddb = 12 v 11740-004 ch1 2.00v ch2 5.00v m40.0ns a ch1 2.20v 2 1 5.00gs/s 100k points ch2 = v ox (5v/div) ch1 = v ix (2v/div) 11740-005 ch1 5.00v ch1 ch2 = ?700.0ps ch1 rise time = 7.870ns ch2 rise time = 7.705ns ch2 5.00v m20.0ns a ch1 2.20v 2 1 5.00gs/s 10m points ch2 = v ob (5v/div) ch1 = v oa (5v/div) 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.25 0.50 0.75 1.00 i dd1 supp l y current (ma) v dd1 = 5.0v v dd1 = 3.3v frequenc y (mhz) 11740-006 0 20 10 30 40 50 0 0.25 0.50 0.75 1.00 i dda /i ddb supp l y current (ma) frequenc y (mhz) v dda /v ddb = 15v v dda /v ddb = 10v v dda /v ddb = 5v 11740-007 0 10 20 30 40 50 60 ?40 ?20 0 20 40 60 80 100 120 pro p ag a tion del a y (ns) junction temper a ture (oc) t dlh t dh l 11740-008 0 10 20 30 40 50 60 3.0 3.5 4.0 4.5 5.0 5.5 pro p ag a tion del a y (ns) input supp l y vo lt age leve l (v) 11740-009 t dlh t dh l rev. a | page 9 of 16
adum7223 data sheet figure 10 . typical propagation delay vs. output supply voltage, v dd1 = 5 v figure 11 . typical rise/fall time vs. output supply voltage figure 12 . typical propagation delay, channel - to - channel matching vs. output supply voltage figure 13 . typical propagation delay (pd) channel - to - channel matching vs. temperature, v dda / v ddb = 12 v figure 14 . typical output resistance vs. output supply voltage figure 15 . typical peak output current vs. output supply voltage, 1.2 series resistance 0 10 20 30 40 50 60 5 7 9 1 1 13 15 17 pro p ag a tion del a y (ns) output supp l y vo lt age (v) t dlh t dh l 11740-010 0 5 10 15 20 25 30 5 7 9 1 1 13 15 17 rise/ f al l time (ns) output supp l y vo lt age (v) t dlh t dh l 11740-011 0 1 2 3 4 5 5 7 9 1 1 13 15 17 pro p ag a tion del a y ch-ch m a tching (ns) output supp l y vo lt age (ns) pd channel- t o-channe l m a tching m a tching t dlh pd channel- t o-channe l m a tching m a tching t dh l 11740-012 ?40 ?20 0 20 40 60 80 100 120 junction temper a ture (oc) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 pro p ag a tion del a y ch-ch m a tching (ns) pd channel- t o-channe l m a tching m a tching t dlh pd channel- t o-channe l m a tching m a tching t dh l 11740-013 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 4.5 7.0 9.5 12.0 14.5 17.0 output resis t ance () output supp l y vo lt age (v) v out source resis t ance v out sink resis t ance 11740-014 0 1 2 3 4 5 6 7 4.5 7.0 9.5 12.0 14.5 17.0 peak current (a) output supp l y vo lt age (v) sink i out source i out 11740-015 rev. a | page 10 of 16
data sheet adum7223 application s i nformation p rinted c ircuit board (pcb) layout the adum7223 digital isolator require s no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins. use a small ceramic capacitor with a value between 0.01 f and 0.1 f to provide a good high frequency bypass. on the output power supply pin s , v dd a or v ddb , it is recommended to add a 10 f capacitor in parallel to provide the charge required to drive the gate capacitance at the adum7223 outputs. lower v alues of de coupling can be used provided the designer ensures that voltage drop s during switching transients are acceptable. the required decoupling is a function of the gate capacitance being driven versus the acceptable voltage drop. o n the output supply pin s, avoi d bypass capacitor use of vias , or employ multiple vias to reduce the inductance in the bypassing. t he total lead length between both ends of the smaller capacitor and the input or output power supply pin must not exceed 20 mm for best performance . for bes t performance, place bypass capacitors as near to the device as possible. propagation delay - related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the propagation delay to a logic low output can differ from the propagation delay to a logic high output. the adum7223 specif ies t dlh as the time between the rising input high logic threshold, v ih , to the out put rising 10% threshold (see figure 16) . likewise, the falling propagation delay, t dhl , is defined as the time between the input falling logic low thr eshold, v il , and the output falling 90% threshold. the rise and fall times are dependent on the loading conditions and are not included in the propagation delay, as is the industry standard for gate drivers. figure 16 . propagatio n delay parameters channel - to - channel matching refers to the maximum amount that the propagation delay differs between channels within a single adum7223 component . propagation delay skew refers to the maximum amount that the propagation delay differs between multiple adum7223 devices operating under the same conditions. thermal limitations and switch load characteristics for isolated gate drivers, the necessary separation between the input and output circuits prevents the use of a single thermal pad beneath the device , and heat is, therefore, dissipated mainly through the package pins. power dissipation within the device is primarily driven by the effective load capacitance being driven, switching frequency, operating voltage, and external series resistance. power dissipation within ea ch channel can be calculated by ( ) gate dson dson sw b dda eff disss r r r f v c p + = 2 / where: c eff is the effective capacitance of the load. v dda/b is the secondary side voltage. f sw is the switching frequency. r dson is the internal resistance of the adum7223 (r oa , r ob ). r gate is the external gate resistor. t o find t emperature rise above ambient temperature, multiply total power dissipation by the ja , which is then added to the ambient temperature to find the approximate internal junction temperature of the adum7223 . each of the adum7223 isolator outputs have a thermal shutdown protection function . this function sets an output to a logic low level when the rising junction temperature typically reache s 150 c and turn s back on after the junction temperature has fallen from the shutdown value by about 10 c. output load characte ristics the adum7223 output signals depend on the characteristics of the output load, which is typically an n - channel mosfet. the driver output response to an n - channel mosfet load can be modeled with a switch output resistance (r sw ), an inductance due to the pcb trac e (l trace ), a series gate resistor (r gate ), and a gate to source capacitance (c gs ), as shown in figure 17. r sw is the switch resistance of the interna l adum7223 driver output (1.1 ? typical for turn - on and 0.6 for turn - off) . r gate is the intrinsic gate resistance of the mosfet and any external series resistance. a mosfet that requires a 4 a gate driver has a typical intrinsic gate resistance of about 1 ? a nd a gate - to - source capacitance ( c gs ) of between 2 nf and 10 nf. l trace is the inductance of the pcb trace, typically a value of 5 nh or less for a well - designed layout with a very short and wide connection from the adum7223 output to the gate of the mosfet. output input t dlh t r 90% 10% v ih v il t f t dhl 1 1740-016 rev. a | page 11 of 16
adum7223 data sheet the following equation defines the q factor of the rlc circuit, which indicates how the adum7223 output responds to a step change. for a well - damped output, q is less than one. adding a series gate resistance dampens the output response. gs trace gate sw c l r r q + = ) ( 1 to reduce output rin ging , add a series gate resistance to dampen the response. for applications using a load of 1 nf or less, add a series gate resistor of about 5 ?. it is recommended that the q factor be below 1 which results in a damped system, with a value of 0.7 as the r ecommended target. figure 17 . rlc model of the gate of an n - channel mosfet dc correctness and m agnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the de coder via the transformer. the decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions of more than 1 s (typical) at the input, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses for more than about 3 s (typical) , the input side is ass umed to be unpowered or nonfunc tional , in which case, the is olator output is forced to a default low state by the watchdog timer circuit. in addition, the outputs are in a low default state while the power is coming up before the uvlo threshold is crossed. the limitation on the adum7223 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. the following analysis defines the conditions u nder which this can occur. the 3 v operating condition of the adum7223 is examined because it represents the most susceptible mode of operation. the pulses at the trans former output have an a mplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, therefore establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = (? d / dt ) ? r n 2 , n = 1, 2, ... , n where: is the magnetic flux density (gauss). r n is the radius of the nth turn in the receiving coil (cm). n is the number of turns in the receiving coil. given the geometry of the receiving coil in the adum7223 and an imposed requirement that the induced voltage is at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated, as shown in figure 18. figure 18 . maximum allowable external magnetic flux density for example, at a magnetic field frequency of 1 mhz, the maxi - mum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. simi - larly, if such an event were to occur during a transmitted pulse ( and had the worst - case polarity), the received pulse is reduced from > 1.0 v to 0.75 v, still well above the 0.5 v sensing thresh - old of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances awa y from the adum7223 transformers. figure 19 expresses these allowable current magnitude s as a function of frequency for selected distances. as shown, the adum7223 is i mmune and only affected by extremely large currents op erated at a high frequency and near the component. for the 1 mhz example, place a 0.5 ka current 5 mm away from the adum7223 to affect the operation of the component . figure 19 . maximum allowable curr ent for various current to adum7223 spacings adum7223 v ia v oa r sw r gate c gs l trace v o 1 1740-017 magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 1 1740-018 magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 1 1740-019 rev. a | page 12 of 16
data sheet adum7223 power consumption the supply current at a given channel of the adum7223 isolator is a function of the supply voltage, channel data rate, and channel output load. for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi ( d ) (2 f C f r ) + i ddi( q) f > 0.5 f r for each output channel, the supply current i s given by i ddo = i ddo ( q ) f 0.5 f r i ddo = (i ddo ( d ) + (0.5) c l v ddo ) (2 f C f r ) + i ddo ( q ) f > 0.5 f r where: i ddi (q) , i ddo (q) are the specified input and output quiescent supply currents (ma). i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). f is the input logic signal frequency (mhz, half of the input data rate, nrz signaling). f r is the input stage refresh rate (mbps). c l is the output load capacitance ( n f). v ddo is the output supply voltage (v). to calculate the total i dd1 and i dd2 supply current, the supply currents for each input and output channel corresponding to i dd1 and i dd2 are calculated and totaled. figure 6 provides tota l input i dd1 supply current as a function of data rate for both input channels. figure 7 provides total i dd2 supply current as a function of data rate for both outputs loaded with 2 nf capacitance. insulation lifetime all insulation structures eventually break down when subjecte d to voltage stress over a sufficiently long period. the rate of insu - lation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog dev ices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the adum7223 . analog devices performs accelerated life testing using voltage level s higher than the rated co ntinuous working voltage. accel eration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 7 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition. in many cases, the approved working voltage is higher than a 50 - year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the adum7223 depends on the voltage waveform type imposed across the is olation barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipo lar ac, or dc. figure 20, figure 21 , and figure 22 illustrate these different isolation voltage waveforms. a bipolar ac voltage environment is the worst case for the i coupler products and is the 50 - year operating lifetime that analog devices recommends for maxim um working voltage. in the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. this allows operation at higher working voltages while still achieving a 50 - year service life. treat a ny cross - insulation voltage waveform th at does not conform to figure 21 or figure 22 as a bipolar ac wave form, and limit its peak voltage to the 50 - year lifetime voltage value listed in table 7 . note that the voltage presented in figure 21 is shown as sinu - soidal for illustratio n purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. figure 20 . bipolar ac waveform figure 21 . unipolar ac waveform figure 22 . dc waveform 0v rated peak voltage 1 1740-020 0v rated peak voltage 1 1740-021 0v rated peak voltage 1 1740-022 rev. a | page 13 of 16
adum7223 data sheet outline dimensions figure 23 . 13- terminal land grid array [lga] (cc - 13- 1) dimensions shown in millimeters ordering guide model 1 no. of channels output peak current (a) minimum output voltage (v) junction temperature range package description package option ordering quantity adum7223accz 2 4 4.5 ? 40c to +125c 13- terminal lga cc-13-1 adum7223accz - rl7 2 4 4.5 ? 40c to +125c 13- terminal lga , 7 tape and reel cc-13-1 1,000 adum7223bccz 2 4 7.5 ? 40c to +125c 13- terminal lga cc-13-1 adum7223bccz - rl7 2 4 7.5 ? 40c to +125c 13- terminal lga , 7 tape and reel cc-13-1 1,000 adum7223cccz 2 4 11.5 ? 40c to +125c 13- terminal lga cc-13-1 adum7223cccz - rl7 2 4 11.5 ? 40c to +125c 13- terminal lga , 7 tape and reel cc-13-1 1,000 eval - adum7223ebz 2 4 4.5 ? 40c to +125c adum7223a evaluation board 1 z = rohs compliant part. 08-21-2013- a top view end view bottom view seating plane 5.10 5.00 sq 4.90 1.00 0.91 0.82 0.175 0.100 0.025 0.475 0.400 0.325 pin 1 corner pin 1 corner 0.70 ref 0.65 bsc 4.15 bsc 3.90 bsc 2.075 1.95 0.21 ref 1 7 8 13 0.65 0.30 pkg-004060 compliant to jedec standards mo-208 rev. a | page 14 of 16
data sheet adum7223 notes rev. a | page 15 of 16
adum7223 data sheet notes ? 2013 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11740 - 0- 4/14(a) rev. a | page 16 of 16

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